Noise canceler for keying pulse in CATV converter

ABSTRACT

A noise canceler for use in a CATV converter includes a keying pulse processing circuit for removing a noise signal from a keying signal. The keying pulse processing circuit includes a canceling signal generator for generating a noise canceling pulse signal, a delaying circuit for delaying the keying signal to produce a delayed signal, and a logic circuit including an AND gate for producing a noise canceled signal which is obtained by taking a logical product of the canceling pulse signal and the delayed signal. Since the noise pulse has a sufficiently small width when compared with the pulse widths of the keying signal and noise removing signal, the noise pulse is removed to obtain a noise canceled signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a keying pulse processing circuit and,more particularly to, a keying pulse processing circuit for use in anoise canceler for a CATV converter.

2. Description of the Prior Art

The keying signal transmitted into the keying, pulse processing circuitis a group of pulse signals having information necessary to descramble ascrambled image signal.

A conventional keying pulse processing circuit will be described withreference to the block diagram shown in FIG. 3. A keying pulse signal S1applied from an input terminal 1 is shaped into a rectangular waveformsignal S2 by a wave shaping circuit 2, and further processed intovarious necessary pulse signals by a pulse processing circuit 3 for usein a video system 4 and CPU 5.

However, in the above conventional set-up of the keying pulse processingcircuit, when a keying signal having a noise signal is input, there hasbeen such a problem that the keying signal is processed without removingthe noise signal from the keying signal, and the processed signal isinput into the next stage as a normal keying signal.

SUMMARY OF THE INVENTION

The object of the present invention is therefore to provide an imagingdevice which solves these problems.

In order to achieve the aforementioned objective, a noise canceler forremoving noise pulses from a keying signal defined by a plurality ofkeying pulses comprises a signal producing means for producing a noisecanceling pulse signal having a canceling pulse in response to a leadingedge of the keying pulse and the noise pulse in the keying signal. Thecanceling pulse had a predetermined pulse width. The noise cancelerfurther comprises a delaying means for delaying the keying signal by apredetermined time to produce a delayed pulse signal, and a cancelingmeans for receiving the canceling signal and the delayed signal anddisabaling the generation of the delayed pulse during the presence ofthe canceling pulse.

BRIEF DESCRIPTION OF THE DRAWINGS

These and to other objects and features of the present invention willbecome clear from the following description taken in conjunction withthe preferred embodiment thereof with reference to the accompanyingdrawings, in which:

FIG. 1a is a block diagram showing a noise canceler according to apreferred embodiment of the present invention;

FIG. 1b is a block diagram showing the details of the noise removalpulse generator of the noise canceler of FIG. 1;

FIG. 2 is a graph showing signals produced and/or processed by the noisecanceler of FIG. 1; and

FIG. 3 is a block diagram showing a conventional keying pulse processingconfiguration.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be describedhereinbelow with reference to the accompanying drawings. Components ofthe same constitution as those in the conventional configuration of FIG.3 will be designated by the same reference number.

Referring to FIG. 1a, a block diagram of a noise canceler according to apreferred embodiment of the present invention is shown. A keying pulseprocessing circuit KC is provided between a wave shaping circuit 2 and apulse processing circuit 3. The wave shaping circuit 2 shapes the keyingsignal S1 transmitted from a terminal 1 into a rectangular wave formsignal S2 taking two alternative levels, "1" and "0". The pulseprocessing circuit 3 processes a noise canceled signal 55 and producesvarious signals for the following stages of a video system 4 and a CPU5.

The keying pulse processing circuit KC comprises a canceling pulsesignal generator 6 for generating a noise removal pulse signal S3 basedon the signal S2, a delaying circuit 7 including a delay circuit, suchas a D flip-flop, for delaying the signal S2 by a predetermined time toproduce a delay signal S4, and a logic circuit 8. The logic circuit 8 isan AND gate having an inverting input terminal and a non-inverting inputterminal for receiving, respectively, the signals S3 and S4, and anoutput terminal. The logic circuit 8 operates to produce a logicalproduct as a noise canceled signal S5 having alterative sleeve, "0" and"1", in accordance with various combinations of "0" and "1" of thesignals S3 and S4, as shown in Table 1, and transmits the producedsignal S5 to the pulse processing circuit 3 through the output terminal.

                  TABLE 1                                                         ______________________________________                                        (Truth Table of Logic Circuit 8)                                              S3         S4    - S- 3       S4  S5                                          ______________________________________                                        1          0     0            0   0                                           1          1     0            1   0                                           0          0     1            0   0                                           0          1     1            1   1                                           ______________________________________                                    

Referring to FIG. 1b, a detail of the canceling pulse signal generator 6is shown. The canceling pulse signal generator 6 includes a leading edgedetector 6a for detecting a leading edge of the signal S2 (a leadingedge of signal S2 described herein is a rising edge), a digital timer 6bwhich times a predetermined time period τ₁ in response to the detectionof the leading edge by the leading edge detector 6a and produces a clearcommand at the termination of the predetermined time period, and a latch6 which latches the signal S2 in response to the receipt of level "1"signal thereof until the clear command is received from the digitaltimer 6b so as to produce a canceling pulse in the canceling pulsesignal S3.

In operation, it is assumed that the keying signal S1 includes a noisepulse, and thus, the keying pulse signal S2 produced from the waveshaping circuit 2 has, as shown in FIG. 2, a keying pulse of a pulsewidth τ and a noise pulse of a pulse width τ_(N). It is to be noted thatτ is greater than τ_(N) (τ>τ_(N)). The canceling pulse signal generator6 produces the canceling pulse signal S3 having a plurality of cancelingpulses, each produced in response to each pulse in the signal S2 andhaving a predetermined width τ₁. It is to be noted that τ₁ is smallerthan τ but greater than τ_(N) (τ>τ₁ >τ_(N)).

The delaying circuit 7 delays the signal S2 by a predetermined time τ₂and produces the delayed keying signal S4 so that a keying pulse of awidth τ and a noise pulse of a width τ_(N) therein are delayed by a timeτ₂ compared with the signal S2. It is to be noted that τ₂ is smallerthan the difference between τ₁ -τ_(N) (τ₂ ≦τ₁ -τ_(N) or τ_(N) ≦τ₁ -τ₂).

The operation of the keying pulse processing circuit KC according to thepresent invention is further described in connection with FIG. 2.

Before time t₁

Because the signal S2 stays at "0", the signals S3 and S4 are both setat "0", according to the Table 1.

From time t₁ to t₂

At time t₁, because the signal S2 changes to "1", the signal S3 is setat "1" in response to the signal S2. However, the signal S4 stays at "0"for the period of τ₂. Therefore, during this period, the signal S5 isset at "0", according to Table 1.

From time t₂ to t₃

At time t₂, i.e. after the time lapse of τ₂ from t₁, the signal S4changes to "1" while the signals S2 and S3 are still at "0". Therefore,the signals S3 and S4 are both at "1", and thus the signal S5 is set at"0", according to Table 1.

From time t₃ to t₄

At time t₃, i.e. after the time lapse of τ₁ from t₁, the signal S3returns to "0", but the signals S2 and S4 stays at "1". Thus the signalS5 is set at "1", according to Table 1.

From time t₄ to t₅

At time t₄, i.e. after the time lapse of τ from t₁, the signals S2returns to "0", while the signals S3 and S4 remain at "0" and "1",respectively. Therefore, the signal S5 is set at "1", according to Table1.

From time t₅ to t₆

At time t₅, i.e. after the time lapse of τ from t₂, the signals S2 andS3 are still at "0", and the signal S4 is set at "0". Therefore thesignal S5 is set at "0", according to Table 1.

From time t₆ to t₇

At time t₆, because the signal S2 as produced from the wave shapingcircuit 2 changes to "1", the signal S3 is set at "1" in response to thesignal S2. The signals S2 and S3 stay at "1" for a period of rxrepresenting a noise pulse width and a period of τ₁, respectively.Therefore, the signal S5 is set at "0", according to Table 1.

From time t₇ to t₇

At time t₇, i.e. after the time lapse of τ₂ from t₆, the signals S2 andS3 are still at "1", and the signal S₄ is set at "1". Therefore, thesignal S5 is set at "0", according to Table 1.

From time t₈ to t₉

At time t₈, i.e. after the time lapse of τ_(N) from t₆, the signal S2returns to "0", but the signals S3 and S4 remain at "1". Thus, thesignal S5 is set at "0", according to Table 1.

From time t₉ to t₁₀

At time t₉, i.e. after the time lapse of τ_(N) from time t₇, the signalsS2 and S3 are still at "0" and "1", respectively, but the signal S4 isset at "0". Therefore, the signal S5 is set at "0", according to Table1.

From time t₁₀ to t₁₁

At time t₁₀, i.e. after the time lapse of τ₁ from t6, the signals S2 andS4 are still at "0", but S3 is set at "0". Therefore, the signal S5 isat "0".

After time t₁₁

At time t₁₀, because the next keying pulse is produced, the pulses ofsignals S1, S2, S3, S4 and S5 become the same as that describedpreviously.

As described above, when a noise pulse having a width τ_(N) less thanthe difference between τ₁ and τ₂ (τ_(N) ≦τ₁ -τ₂) is included in thekeying signal S1, such a noise pulse is eliminated from the noisecanceled keying signal S5 generated by the keying pulse processingcircuit KC of the present invention.

According to the above embodiment, the noise canceled signal S5 isdelayed by the delay time τ₂, and the leading edge of the keying pulsestherein is delayed by an amount of τ₁ when compared with the keyingsignal S4. In the case where such delays adversely affect the operation,the delay τ₂ can be counterbalanced with a suitable phase advancingdevice inserted in a transmission system and the problem of the delay τ₁can be eliminated by using the trailing edge, instead of the leadingedge, as a reference for processing the signal in the processing system.

As described hereinabove, it is possible to provide a keying pulseprocessing circuit KC which can remove the noise pulses having a pulsewidth less than a predetermined pulse width (τ₁ -τ₂) with a very simpleconstruction without using a waveform memory or a feed-back system.Thus, it is possible to realize a circuit which can operate at a highspeed and is suitable for an integrated circuit.

Although the present invention has been fully described in connectionwith the preferred embodiments thereof with reference to theaccompanying drawings, it is to be noted that various changes andmodifications are apparent to those skilled in the art. Such changes andmodifications are to be understood as included within the scope of thepresent invention as defined by the appended claims unless they departtherefrom.

What is claimed is:
 1. A noise canceler for removing noise pulses from akeying signal defined by a plurality of keying pulses and noise pules,comprising:a canceling pulse generating means for receiving the keyingsignal and for generating a canceling pulse signal having a cancelingpulse upon each leading edge of each keying pulse and noise pulse of thekeying signal, each canceling pulse having a pulse width of a firstpredetermined time period; a delaying means for receiving the keyingsignal and for delaying each keying pulse and noise pulse of the keyingsignal by a second predetermined time period to generate a delayedkeying signal; and, a canceling means for receiving said delayed keyingsignal from said delaying means and said canceling pulse signal fromsaid canceling pulse generating means, and for generating a noisecanceled keying signal having a pulse corresponding to each receivedpulse of said delayed keying signal except during a time period in whicha canceling pulse of said canceling pulse signal is also received; saidcanceling pulse generating means including (a) a leading edge detectorfor detecting a leading edge of each keying pulse and noise pulse ofsaid keying signal, (b) a timer, coupled to said leading edge detector,for generating a clear signal after the lapse of said firstpredetermined time period from the detection of a leading edge by saidleading edge detector, and (c) a latch circuit, coupled to said timer,for latching said keying signal to generate a first level signal at eachkeying pulse and noise pulse of said keying signal and for clearing inresponse to said clear signal from said timer to generate a second levelsignal, said first level signal corresponding to a canceling pulse.
 2. Anoise canceler as recited in claim 1, wherein said canceling meanscomprises an AND gate having an inverting input terminal receiving saidcanceling pulse signal, a non-inverting input terminal receiving saiddelayed keying signal, and an output terminal for generating a logicalproduct of the inverted canceling pulse signal and the non-inverteddelayed keying signal.